1. Field of the Invention
The present invention generally relates to semiconductor memory cell structures and fabrication methods therefore and, more particularly, to methods of fabrication and a structure for a contacted-body silicon-on-insulator (SOI) dynamic random access memory (DRAM) which uses deep trench storage capacitors and field-shield isolation.
2. Background Description
As operating voltages are reduced, it becomes increasingly challenging to write a usable high level into a DRAM storage capacitor because of the limiting effects of subthreshold slope and substrate sensitivity. Threshold voltage has become essentially unscalable with bulk metal oxide semiconductor field effect transistors (MOSFETs) operating at room temperature, since minimum threshold voltage is determined by off-current requirements and subthreshold slope, not with operating voltage or geometry. Furthermore, device substrate sensitivity increases the threshold voltage and compounds the loss of overdrive during writeback of a high level.